Disabling vector grouping for RVV


I’m currently working on a proof of concept hardware to run RISC-V Vector Extension, and I do not plan on supporting vector grouping at the moment. Is there any way (i.e. flag) to tell clang NOT to utilize vector grouping (e.g. always have LMUL = 1)?

I was able to achieve the desired effect (LMUL = 1) using the flags:


Which sets the max LMUL to 1, BUT that is not enough as the compiler seems to still use LMUL=2 in some sections of my code, and after some investigation I found that this was due to LLVM using ‘scalable vectors’ which I could turn off using the following flag:


These flags forced the highest LMUL to be 1, but they permitted lower LMULs (e.g. 1/4) which I did not want to support at the moment. To overcome this I found the flag:


Which, from my understanding, tells the compiler how many elements to put into one vector. Since I was dealing with 128-bit vectors and 8-bit elements, a vector width of 16 caused the compiler to use only one vector register at a time (LMUL = 1) at all times. I think using this flag overrides the two previous flags and makes them redundant.

If anyone has a better approach to this I would love to hear it