Below is the performance and code size ratio of SPEC2017.
Table 1 shows the observed performance impact of the MCU on the specint2017 and specfp2017 benchmark suite when compiled with LLVM compiler. The columns labeled HW show that there is ~2% performance loss as measured by the geomean. Performance loss on individual components was observed to be as high as 7%.
Software-based tools to mitigate these effects are being developed and are outlined below. From our experiments, recompiling the benchmarks recovered the geomean performance to within 99% of the originally observed performance, and the maximum performance loss in SPEC benchmarks was subsequently reduced to within 4% of the original performance.
We also measured the increase in code size due to the addition of padding to instructions to align branches correctly (Table 2). The geomean increase in code size is 2-3% with individual outliers of up to 4%.
Table 1 - SPEC2017 SW/HW mitigation vs. baseline performance ratio:
test SW vs baseline HW vs baseline HW+SW vs baseline
500.perlbench_r 0.97 0.97 0.96
502.gcc_r 1.00 0.99 0.99
505.mcf_r 1.00 0.97 1.01
520.omnetpp_r 1.00 0.99 0.99
523.xalancbmk_r 0.99 0.99 0.99
525.x264_r 1.00 0.96 0.99
531.deepsjeng_r 1.00 0.98 0.99
541.leela_r 1.00 1.00 1.00
557.xz_r 1.02 0.95 1.02
SIR 1.00 0.98 0.99
508.namd_r 1.00 0.99 1.00
510.parest_r 1.00 1.00 1.01
511.povray_r 1.02 0.96 1.02
519.lbm_r 1.00 1.01 1.00
526.blender_r 0.99 0.93 1.00
538.imagick_r 0.99 0.99 1.00
544.nab_r 1.00 0.98 1.00
FIR 1.00 0.98 1.00
Table 2 - SPEC2017 SW/HW mitigation vs. baseline Code Size ratio:
test baseline SW
500.perlbench_r 1 1.04
502.gcc_r 1 1.04
505.mcf_r 1 1.02
520.omnetpp_r 1 1.04
523.xalancbmk_r 1 1.03
525.x264_r 1 1.02
531.deepsjeng_r 1 1.02
541.leela_r 1 1.03
557.xz_r 1 1.03
SIR Geomean 1 1.03
508.namd_r 1 1.01
510.parest_r 1 1.03
511.povray_r 1 1.02
519.lbm_r 1 1.01
526.blender_r 1 1.03
538.imagick_r 1 1.03
544.nab_r 1 1.03
SFR Geomean 1 1.02
Test date:
2019/11/10
System Configuration:
OS: Red Hat* 8.0 x86_64
Memory: 191 GB
CPUCount: 2
CoreCount: 40
Intel HyperThreading: yes
CPU Model: Intel(R) Xeon(R) Gold 6148 CPU @ 2.40GHz
Microcode w/o hw mitigation: 0x200005e
Microcode with hw mitigation: 0x2000063
Compiler options:
unmitigated: -march=skylake-avx512 -mfpmath=sse -Ofast -funroll-loops –flto
mitigated: -march=skylake-avx512 -mfpmath=sse -Ofast -funroll-loops –flto -Wl,-plugin-opt=-x86-branches-within-32B-boundaries
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Baseline means the system w/o MCU mitigation and w/o SW mitigation.
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SW means prefix mitigation is applied to a Non MCU system.
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HW means the MCU mitigation is applied w/o SW mitigation.
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HW+SW means both MCU and prefix mitigations are applied.
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LLVM measurements are only limited to C/C++ benchmarks. All Fortran benchmarks are excluded.
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The test is done on an engineering build plus the SW mitigation patch. It may be variant from build to build.
##Disclaimer:
For more complete information about performance and benchmark results, visit Overview - 1 | Performance Indexhttp://www.intel.com/benchmarks. For specific information and notices/disclaimers regarding the Jump Conditional Code Erratum, visit https://www.intel.com/content/dam/support/us/en/documents/processors/mitigations-jump-conditional-code-erratum.pdf.