Dump instruction list prior register allocation

Hi there,

I have a question on the LLVM internals.

Is it possible to dump an InstructionList (i.e. a (possibly) naively scheduled
assembly) prior register allocation? Does LLVM use infinite (virtual) registers
similar to MachSUIF? This is, of course, meant for a given target in contrast
to MachSUIF that features the SUIFvm ISA as low-level IR and such a dump is
possible at this point.

Plus:

How do things progress towards LLVM following release. Is Oct 31, a probable
date for the release? What about LLVM-TV, is it going to be included.

Nikolaos Kavvadias
<nkavv-at-physics-dot-auth-dot-gr>

I have a question on the LLVM internals.

Is it possible to dump an InstructionList (i.e. a (possibly) naively scheduled
assembly) prior register allocation?

Sure, the -print-machineinstrs flag does this for LLC today.

Does LLVM use infinite (virtual) registers
similar to MachSUIF? This is, of course, meant for a given target in contrast
to MachSUIF that features the SUIFvm ISA as low-level IR and such a dump is
possible at this point.

Yes, it does. It uses virtual registers in SSA form before register allocation. There is some info about this here:
http://llvm.cs.uiuc.edu/docs/CodeGenerator.html#codegendesc

How do things progress towards LLVM following release. Is Oct 31, a probable
date for the release?

We basically keep doing development and ocassionally do releases. We originally aimed to do releases every 3 months, but for various reasons, we fell behind schedule. Oct31 is the target date for starting the release process. I would guess a release will roll out a week after that.

What about LLVM-TV, is it going to be included.

Probably not. It doesn't receive much love and attention. If you'd like to make sure it still works, we can figure out how to package it with the release though.

-Chris