DWARF Register Mapping in SysV-x86_64 ABI

Hello Greg

I was going through the code of x86_64 SysV ABI implementation (ABISysV_x86_64.cpp). I noticed one thing that DWARF Register Number mapping is not in conformance with the SysV-ABI Specification document for x86_64. The reference document I am using is “System V Application Binary Interface, AMD64 Architecture Processor Supplement, Draft Version 0.99.6, October 7, 2013”.

I hope the register number mapping is present in the enum “gcc_dwarf_regnums”. I don’t know whether I am missing something here but can you throw some light on it ?

Abhishek Aggarwal

We match everything except ymm8-ymm15 and we are missing all register entries that follow mm7, but those aren't ever used in any DWARF expressions locations that our compilers generate, so we haven't needed those definitions.

If you want to see what clang uses you can checkout:

svn cat http://llvm.org/svn/llvm-project/llvm/trunk/lib/Target/X86/X86RegisterInfo.td

What registers are you worried about? Feel free to add any register x86_64 dwarf definitions that are in the spec and missing from our gcc_dwarf_regnums, but don't remove or change any that are already there.

Greg Clayton

In the ABI Specification document, mm0-mm7 registers have been assigned separate numbers than st0-st7 while gcc_dwarf_regnums misses the entries for mm0-mm7 altogether.

Are you talking about the register numbering in ABISysV_x86_64.cpp? There's the same numbering issue in debugserver's DNBArchImplX86_64.cpp. RegisterContextDarwin_x86_64.cpp too.

RegisterContext_x86.h has the correct numbers. I think RegisterInfos_x86_64.h will create separate mm0-7 and st0-7 register entries?

I agree that we should use the correct dwarf #'s from the SysV ABI doc. I have a low priority bug tracking the fact that lldb should display "st0-7" and "mmx0-7" registers separately to the user even though they occupy the same part of the register file -- formatting them as floats vrs. vector of uint8_t's by default or something. The kernel on Mac OS X refers to this part of the register file as "stmm0-7" and lldb just picked up that same name convention but it's not at all what an x86 programmer would expect.

I'm not sure about some of these register files which list ymm dwarf register numbers, even for the upper half. Intel has an update to the SysV ABI doc, newest I've found is v0.3 from 2013-07-17 at

and in section 3.2.1 ("Registers and the Stack Frame") it says, "For purposes of parameter passing and function return, %xmmN, %ymmN and %zmmN refer to the same register. Only one of them can be used at the same time. We use vector register to refer to either SSE, AVX or AVX-512 register. In addition, Intel R AVX-512 also provides 8 vector mask registers (%k0 - %k7), each 64bits wide." And in figure 3.38 ("DWARF Register Number Mapping"), it only specifies register numbers for xmm0-7 ("Vector Registers"), xmm8-15 ("Extended Vector Registers"), and xmm16-31 ("Upper Vector Registers").