Enabling vectorization with LLVM 3.3 for a DSL emitting LLVM IR

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#1

Hi,

For libfaust, perhaps? :slight_smile:

Could it be something as simple as a target triple defined for the module? Without knowledge of the target machine vector width, the vectorizer will assume maximum width of 1. You can override this without a triple by using the -force-vector-width switch.

Vesa