Error in a custom analysis Pass


I am writing an analysis pass for a custom processor. I get an unusual
situation where the code generated for a BB is

BB#23: derived from LLVM BB %sw.bb99
    Live Ins: %vr2 %vr0 %vr1 %vr9 %vr3 %vr8 %vr4 %vr5 %vr6
    Predecessors according to CFG: BB#22
        %vr46<def> = LD_Iri %LV, -4; mem:LD4[FixedStack0]
        %vr7<def> = ADDri %vr9, 1
        %vr47<def> = ADDri %vr46, -4
        ST_Iri %LV, -4, %vr47<kill>; mem:ST4[%cpArg.addr]
>>> %vr48<def> = LD_Iri %vr46<kill>, 0; mem:LD4[<unknown>]
        ST_Cri %vr9<kill>, 0, %vr48<kill>; mem:ST1[%cpStrBuf.1]
        %vr8<def> = ADDri %vr8<kill>, 1
        JUMP <BB#1>
    Successors according to CFG: BB#1

The instruction

%vr48<def> = LD_Iri %vr46<kill>, 0; mem:LD4[<unknown>]

seems to be a load instruction with a memory location unknown. Can
anyone help me point out, what can be the possible reason. This code
has been generated for

(gdb) print QueryInst->getParent()->getBasicBlock()->dump()

sw.bb99: ; preds = %if.end40
  %2 = va_arg i8** %cpArg.addr, i32
  %conv100 = trunc i32 %2 to i8
  store i8 %conv100, i8* %cpStrBuf.1
  %ptrincdec104 = getelementptr inbounds i8* %cpStrBuf.1, i32 1
  br label %for.inc445

The code for lowering va_arg is not written by me. So, I don't fully
understand it. It is similar to code used for ARM be.

I just need some pointers which can help me to start with the
debugging the problem. I shall be grateful for any help.