What do these mean and what should I do to address them?
[error] [firtool] Running "firrtl.module(cse, firrtl-lower-chirrtl)"
[error] [firtool] -- Done in 4.396 sec
[error] [firtool] Running "firrtl-infer-widths"
[error] [firtool] -- Done in 6.488 sec
[error] [firtool] Running "firrtl-infer-resets"
[error] [firtool] -- Done in 4.708 sec
[error] [firtool] Running "firrtl-dedup"
[error] [firtool] -- Done in 9.918 sec
[error] [firtool] Running "firrtl-dft"
[error] [firtool] -- Done in 0.681 sec
[error] [firtool] Running "firrtl-prefix-modules"
[error] [firtool] -- Done in 0.978 sec
[error] [firtool] Running "firrtl-lower-types{flatten-mem=false preserve-aggregate=false preserve-public-types=true}"
[error] [firtool] -- Done in 2.348 sec
[error] [firtool] Running "firrtl.module(firrtl-expand-whens, firrtl-remove-resets, canonicalize{ max-iterations=10 region-simplify=true top-down=true})"
[error] [firtool] -- Done in 5.685 sec
[error] [firtool] Running "firrtl-inliner"
[error] [firtool] -- Done in 2.876 sec
[error] [firtool] Running "firrtl-imconstprop"
[error] [firtool] -- Done in 5.253 sec
[error] [firtool] Running "firrtl-blackbox-reader{input-prefix= resource-prefix=}"
[error] [firtool] -- Done in 0.052 sec
[error] [firtool] Running "firrtl.module(canonicalize{ max-iterations=10 region-simplify=true top-down=true})"
[error] [firtool] -- Done in 1.134 sec
[error] [firtool] Running "firrtl-remove-unused-ports"
[error] [firtool] -- Done in 0.609 sec
[error] [firtool] Running "firrtl-emit-metadata{repl-seq-mem=false repl-seq-mem-circuit= repl-seq-mem-file=}"
[error] [firtool] -- Done in 0.027 sec
[error] [firtool] Running "firrtl-emit-omir{file=}"
[error] [firtool] -- Done in 0.000 sec
[error] [firtool] -- Done in 45.155 sec
[error] [firtool] Running "lower-firrtl-to-hw{error-on-non-const-async-reset-values=true warn-on-unprocessed-annotations=true}"
[error] <stdin>:1:1: warning: unprocessed annotation:'firrtl.stage.RunFirrtlTransformAnnotation' still remaining after LowerToHW
[error] circuit FooTop :
[error] ^
[error] <stdin>:93:10: warning: unprocessed annotation:'firrtl.passes.wiring.SourceAnnotation' still remaining after LowerToHW
[error] module FooInterfaceUnit :
[error] ^
[error] <stdin>:503233:10: warning: unprocessed annotation:'firrtl.passes.wiring.SinkAnnotation' still remaining after LowerToHW
[error] module FooTop :
[error] ^
[error] [firtool] -- Done in 3.576 sec
[error] [firtool] Running "hw-memory-sim{ignore-read-enable-mem=false repl-seq-mem=false}"
[error] [firtool] -- Done in 0.005 sec
[error] [firtool] Running "sv-extract-test-code"
[error] [firtool] -- Done in 0.462 sec
[error] [firtool] Running "hw.module(cse, canonicalize{ max-iterations=10 region-simplify=true top-down=true}, hw-cleanup)"
[error] [firtool] -- Done in 1.822 sec
These aren’t actually “errors”, but are printed to stderr. All of the “running”/“done” is just information about what is running. This is shown if you run with --verbose-pass-executions. The other warnings are indicating that during the conversion from FIRRTL to HW dialects there were still annotations remaining. This indicates that you may have divergence from the SFC due to unsupported features. (I’m this case that indicates that the wiring transform annotations weren’t processed because the wiring transform has not been ported to CIRCT.)
Ah, I see.
Is there any sort of timeframe on when these transforms will be supported?
No time frame and there’s nobody working on this right now. Our main effort has been two-fold to this point: (1) build a minimal FIRRTL compiler that supports every standard/non-optional transformation from Chisel to Verilog and (2) add support for all internal and external custom transforms that SiFive uses. (2) has resulted in big new features, e.g., --extract-test-code (to pull all asserts/assumes/covers into bindable modules), sifive.enterprise.firrtl.FullAsyncResetAnnotation (to add async resets to every register under a module that do not have a reset), or “Grand Central” (a mechanism to construct SystemVerilog interface “views” of anything in the design and wire these up via XMRs).
The rough plan is to release a Chisel 3.6 that upstreams sifive/chisel-circt to enable compilation with either FIRRTL compiler. Simultaneously, we will start having Chisel 3.7 milestone releases that drop Scala FIRRTL Compiler support. At that point, we then keep this Chisel 3.6/Chisel 3.7 split going while lingering features that people want are ported (ideally by the people that want them 
) into Chisel 3.7/CIRCT.
The corollary here is that we could use help in areas where there are custom transforms/Chisel APIs that people care about and want to continue to use.
For something like BoringUtils, this is actually an awesome opportunity as it allows us to dramatically improve the API and implementation. E.g., BortingUtils.bore makes a lot of sense, but the implementation of BoringUtils.source/sink are extremely janky in the SFC. The WiringTransform has to infer ownership of sources to sinks to figure out what the user meant. Similarly, BoringUtils is really a subset of what a user could want to do with this API. I.e., this is really a Chisel-level mechanism for describing XMRs and a mandatory lowering of these into hard connections. The ideal API is that this describes XMRs and then those XMRs may or may not be lowered into hard connections.
We sincerely hope that there are some “big carrots” to motivate migration to CIRCT (speed, big new features, enterprise-strength compiler infrastructure on top of which users can build large open or proprietary value additions). We also recognize that there will be some speed bumps here.
Expect more communication about this in the future. In the mean time, feel free to continue this dicussion here or reach out to me directly.
Thanks!
I need to use BoringUtils with Bundles, which leads me to use interfaces other than BoringUtils.bore().
If Chisel supported BoringUtils.bore() with Bundles, I could get rid of that cruft.