I hope you don't mind if my question is a little off topic, but I have been using LLVM to do register allocation for the x86 aliased register bank, and now I want to find more applications for my algorithm. So, I wish I could find an example of a computer architecture with more than two level of aliasing in the register bank. For instance, SPARC has 16 floating point registers that can be further divided into 32 single precision registers. Is there an example of an architecture that allows registers to be divided into two, four or more smaller registers? I thought at first in MMX, but the MMX instructions do not let me access each subregister independently.
Please, let me now if this was too off-topic, and then I will not write it again.