Some verilog always block includes the automatic logic.
Below the code generated from the firtool.
always @(posedge clock) begin // Monitor.scala:397:15
automatic logic _T_12; // Monitor.scala:396:20
automatic logic _T_13; // Monitor.scala:549:20
_T_12 = _T_2 & ~(|a_first_counter); // Edges.scala:229:28, :230:25, Monitor.scala:396:20
_T_13 = _T_3 & ~(|d_first_counter); // Edges.scala:229:28, :230:25, Monitor.scala:549:20
opcode <= _T_12 ? io_in_a_bits_opcode : opcode; // Monitor.scala:390:32, :397:15
param <= _T_12 ? io_in_a_bits_param : param; // Monitor.scala:391:32, :398:15
size <= _T_12 ? io_in_a_bits_size : size; // Monitor.scala:392:32, :399:15
source <= _T_12 ? io_in_a_bits_source : source; // Monitor.scala:393:32, :400:15
address <= _T_12 ? io_in_a_bits_address : address; // Monitor.scala:394:32, :401:15
opcode_1 <= _T_13 ? io_in_d_bits_opcode : opcode_1; // Monitor.scala:542:29, :550:15
param_1 <= _T_13 ? io_in_d_bits_param : param_1; // Monitor.scala:543:29, :551:15
size_1 <= _T_13 ? io_in_d_bits_size : size_1; // Monitor.scala:544:29, :552:15
source_1 <= _T_13 ? io_in_d_bits_source : source_1; // Monitor.scala:545:29, :553:15
sink <= _T_13 ? io_in_d_bits_sink : sink; // Monitor.scala:546:29, :554:15
denied <= _T_13 ? io_in_d_bits_denied : denied; // Monitor.scala:547:29, :555:15
end // always @(posedge)
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When running the yosys with the command "read_verilog ", it prints as below
“ERROR : syntax error, unexpected TOK_AUTOMATIC”
What I know of on the keyword automatic in the systemverilog, it must be used in the procedural context. But it seems some “automatic logic” declaration is used in the different context.
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Also the consistency in the always block shall be fixed. In the above block, the non-blocking assignment and the blocking assignment are in the same always block which seems not quite right.
thanks for the report - I believe the = issue is fixed as of last night.
That said, I’m not sure what to do if yosys doesn’t like automatic logic declarations in an always block - is there some other way to declare local values that it is compatible with?
I am afraid not.
What most verilog mandate is declaring the variable when the verilog module starts.
So in the previous case, it would seems like this.
logic _T_12; // Monitor.scala:396:20
logic _T_13; // Monitor.scala:549:20
always @(posedge clock) begin // Monitor.scala:397:15
_T_12 = _T_2 & ~(|a_first_counter); // Edges.scala:229:28, :230:25, Monitor.scala:396:20
_T_13 = _T_3 & ~(|d_first_counter); // Edges.scala:229:28, :230:25, Monitor.scala:549:20
opcode <= _T_12 ? io_in_a_bits_opcode : opcode; // Monitor.scala:390:32, :397:15
param <= _T_12 ? io_in_a_bits_param : param; // Monitor.scala:391:32, :398:15
size <= _T_12 ? io_in_a_bits_size : size; // Monitor.scala:392:32, :399:15
source <= _T_12 ? io_in_a_bits_source : source; // Monitor.scala:393:32, :400:15
address <= _T_12 ? io_in_a_bits_address : address; // Monitor.scala:394:32, :401:15
opcode_1 <= _T_13 ? io_in_d_bits_opcode : opcode_1; // Monitor.scala:542:29, :550:15
param_1 <= _T_13 ? io_in_d_bits_param : param_1; // Monitor.scala:543:29, :551:15
size_1 <= _T_13 ? io_in_d_bits_size : size_1; // Monitor.scala:544:29, :552:15
source_1 <= _T_13 ? io_in_d_bits_source : source_1; // Monitor.scala:545:29, :553:15
sink <= _T_13 ? io_in_d_bits_sink : sink; // Monitor.scala:546:29, :554:15
denied <= _T_13 ? io_in_d_bits_denied : denied; // Monitor.scala:547:29, :555:15
end // always @(posedge)
Also what I know of on the verilog, they don’t have the local variable concept in the always block.
So when the hardware programmer first learn the verilog programming language and tries the commercial verilog compiler, they have to declare the wire, reg, local variable at the first of the module, and then uses the wire in assign statement, the reg in always block.
Ok, thanks. I filed this ticket to track this, I’ll take a look when I can.