Firtool - removing unused definitions from every .sv file

The code below is output in every .sv file, whether it is used or not.

Is there a way to tell firtool not to output this?

// Users can define 'ASSERT_VERBOSE_COND' to add an extra gate to assert error printing.
    `define ASSERT_VERBOSE_COND_ 1
`endif // not def ASSERT_VERBOSE_COND_

// Users can define 'STOP_COND' to add an extra gate to stop conditions.
`ifndef STOP_COND_
  `ifdef STOP_COND
    `define STOP_COND_ (`STOP_COND)
  `else  // STOP_COND
    `define STOP_COND_ 1
  `endif // STOP_COND
`endif // not def STOP_COND_

Yeah this is definitely something that shouldn’t be emitted if the SV itself doesn’t contain any references to these macros. We are doing a similar thing for register randomization, where the macros should only be emitted if the design contains any registers.

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