The code below is output in every .sv file, whether it is used or not.
Is there a way to tell firtool not to output this?
// Users can define 'ASSERT_VERBOSE_COND' to add an extra gate to assert error printing.
`define ASSERT_VERBOSE_COND_ (`ASSERT_VERBOSE_COND)
`else // ASSERT_VERBOSE_COND
`define ASSERT_VERBOSE_COND_ 1
`endif // ASSERT_VERBOSE_COND
`endif // not def ASSERT_VERBOSE_COND_
// Users can define 'STOP_COND' to add an extra gate to stop conditions.
`define STOP_COND_ (`STOP_COND)
`else // STOP_COND
`define STOP_COND_ 1
`endif // STOP_COND
`endif // not def STOP_COND_
Yeah this is definitely something that shouldn’t be emitted if the SV itself doesn’t contain any references to these macros. We are doing a similar thing for register randomization, where the macros should only be emitted if the design contains any registers.
I tested this in firtool 1.48.0, it still happens. I was about to repost the question because I forgot that I had asked before… Instead I decided to update this topic.
--emit-chisel-asserts-as-sva to firtool, then these definitions are not inserted.
I can now choose to emit .sv files that are stripped of randomization, assertions, etc. which can be helpful when working on the backend flow, less to wade through…