I recently filed this bug: http://llvm.org/bugs/show_bug.cgi?id=8323
It's a dodgy one because you have to patch LLVM to demonstrate it.
I suspect that the cause of the problem in that "bug" is that the
peephole optimisation in PerformDAGCombine results in a Flag output
from one node being used as input by two other nodes in the DAG, and
the scheduler then can't cope with that.
Is it, or should it be legal for a Flag output to be used as input by
more than one other node?
If it is legal, does it ever actually work, and, if not, is there
already a bug filed relating to this?
If it isn't legal, are there sufficient guarantees that it won't
happen, and could we please have a better error message if it does
happen by accident?
In either case, how should the following code get translated in such a
way that we don't repeat the comparison?
int f1(int x)
{
return x < 0 ? 11 : x == 0 ? 22 : 33;
}
Currently, with the ARM back end, I'm getting "cmp r0, #0" repeated.
Replace 0 by 100 and I get two instances of "cmpl $100, %edi" in the
x86 output, too.
Is there already a bug filed relating to that missed optimisation?
(Bug 7592 is related to it.)
Thanks,
Edmund