GCC and dwarf equivalent register numbers in x86

Hi,

In the qRegisterInfo packet (in the gdb remote protocol), I was wondering where does LLDB get the dcc/dwarf corresponding register numbers from.

While looking at the gcc source file for the register numbers:
https://raw2.github.com/mirrors/gcc/master/gcc/config/i386/i386.c

I saw a discrepancy between lldb numbering and gcc in 32bit. In:
http://llvm.org/svn/llvm-project/lldb/trunk/source/Plugins/ABI/MacOSX-i386/ABIMacOSX_i386.cpp

The ymm registers are mapped to the xmm registers:


dwarf_ymm0 = dwarf_xmm0

And I can’t find a similar mapping in the i386.c posted above (in the svr4_dbx_register_map which is used to describe the dwarf numbering).

IIRC the "gcc" register numbers exist to work around one ancient bug in gcc's i386 eh_frame register numbering. There was a gcc release that mixed up the register numbers in the eh_frame section (ebp and esp were swapped) and everyone has had to special-case this since.

The "gdb" register numbers are the numbers used in the stabs debug format by gcc & gdb.

The DWARF register numbers are defined by process/ABI specific documents. For the SysV ABI on x86_64, this is the

  System V Application Binary Interface
  AMD64 Architecture Processor Supplement
  Draft Version 0.99.6
  Edited by Michael Matz, Jan Hubicka, Andreas Jaeger, Mark Mitchell
  July 2, 2012

(that's the most recent version I've ever found). There's a newer variant of the doc that Intel put out to update for some of the new register sets,

  System V Application Binary Interface
  AMD64 Architecture Processor Supplement
  (With LP64 and ILP32 Programming Models)
  Draft Version 0.3
  Edited by Michael Matz, Jan Hubicka, Andreas Jaeger, Mark Mitchell
  Edited for Intel AVX, Intel AVX2, Intel AVX-512 and Intel MPX specific conventions by Milind Girkar, Hongjiu Lu,
David Kreitzer, Vyacheslav Zakharin
  July 17, 2013

anyway, either version of this standard includes a DWARF Register Number Mapping table which tells us that xmm0-xmm7 is 17-24 and xmm8-xmm15 is 25-32 and in the "Registers and the Stack Frame" section we find the comment about ymm, "Intel AVX (Advanced Vector Extensions) provides 16 256-bit wide AVX reg- isters (%ymm0 - %ymm15). The lower 128-bits of %ymm0 - %ymm15 are aliased to the respective 128b-bit SSE registers (%xmm0 - %xmm15). For purposes of parameter passing and function return, %xmmN and %ymmN refer to the same register. Only one of them can be used at the same time. We use vector register to refer to either SSE or AVX register."

(I know you're asking about i386 and I'm posting a doc about x86_64 but I couldn't find an authoritative source for i386 DWARF register number mapping right away and I gave up looking.)