Getting the size of a type in SystemVerilog

This is a continuation of the comments in this PR about where and how we should do this. Comments reproduced here:

Code comment:

/// Figure out the number of bits a type takes on the wire in verilog. Doing it
/// here is probably a giant hack. TODO: Establish a canonical method to get
/// this information.

@clattner I think it would make sense to have a global function in RTL/Types.h. It’s not clear what this will mean with extensible types though.

@mikeurbach I’ve been thinking about this too, since I’ve been looking at getBitWidthOrSentinel in EmitVerilog. Maybe there could be an type interface that could let the types declare the width (or lack thereof)? I’ve never used a type interface, but it seems like that could be a good fit for an open type system.

Me (John): The RTL dialect, not the SV dialect? I was thinking SV since the number of bits is technically a SystemVerilog thing (other dialects which lower from RTL could represent types differently). Putting it in the SV dialect could solve the extensibility issue since it is reasonable for the SV dialect to have a closed type system.