[GISel] how to add the regbank for a const value

Allen · July 8, 2023, 7:53am

hi,
When I create a new vector const with following code, I’ll get a MachineInstr %0:(<2 x s32>) = G_BUILD_VECTOR %1:(s32), %2:_(s32) missing regbank information, this is different from the normal format %0:fpr(<2 x s32>) = G_BUILD_VECTOR %1:gpr(s32), %2:gpr(s32), so how to add related regbank information or is the wrong interface used ?

const LLT S32 = LLT::scalar(32);
const LLT DstTy = LLT::fixed_vector(2, S32)；
APInt Simm0 = APInt(32, 0);
APInt Simm1 = APInt(32, 1);

auto Concat = MIB.buildBuildVectorConstant(DstTy, {Simm0，Simm1});

Allen · July 8, 2023, 9:33am

oh, the regbank will be added with setRegBank, but it still report
LLVM ERROR: VReg has no regclass after selection: %3:fpr(<2 x s32>) = G_BUILD_VECTOR %4:gpr(s32), %6:gpr(s32) in InstructionSelect

auto C0 = MIB.buildConstant(S32 , 0);
MRI.setRegBank(C0.getReg(0), RBI.getRegBank(AArch64::GPRRegBankID));
auto C1 = MIB.buildConstant(S32 , 1);
MRI.setRegBank(C1.getReg(0), RBI.getRegBank(AArch64::GPRRegBankID));

auto Concat2 = MIB.buildBuildVector(DstTy, {C0.getReg(0), C1.getReg(0)});

Allen · July 10, 2023, 3:48am

Even for the simple case, I only try to add a unused node, it still report the similar issue.
LLVM ERROR: VReg has no regclass after selection: %4:gpr(s32) = G_CONSTANT i32 0

const LLT S32 = LLT::scalar(32);
auto C0 = MIB.buildConstant(S32 , 0);
MRI.setRegBank(C0.getReg(0), RBI.getRegBank(AArch64::GPRRegBankID));

Allen · July 10, 2023, 6:37am

New error unknown operand type in function lowerOperand because the const type is “MachineOperand::MO_CImmediate” after adding MRI.setRegClass(C0.getReg(0), &AArch64::GPR64RegClass) to fix above " LLVM ERROR: VReg has no regclass after selection"

282	bool AArch64MCInstLower::lowerOperand(const MachineOperand &MO,
283	                                      MCOperand &MCOp) const {
284	  switch (MO.getType()) {
285	  default:
286	    llvm_unreachable("unknown operand type");

This is because the buildConstant bring in addCImm.

github.com

llvm/llvm-project/blob/ac6ea22f4ce42ec371412ddcbcbe259128149fb8/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp#L327


      
            if (Ty.isVector()) {
              auto Const = buildInstr(TargetOpcode::G_CONSTANT)
              .addDef(getMRI()->createGenericVirtualRegister(EltTy))
              .addCImm(&Val);
              return buildSplatVector(Res, Const);
            }
          
            auto Const = buildInstr(TargetOpcode::G_CONSTANT);
            Const->setDebugLoc(DebugLoc());
            Res.addDefToMIB(*getMRI(), Const);
            Const.addCImm(&Val);
            return Const;
          }
          
          MachineInstrBuilder MachineIRBuilder::buildConstant(const DstOp &Res,
                                                              int64_t Val) {
            auto IntN = IntegerType::get(getMF().getFunction().getContext(),
                                         Res.getLLTTy(*getMRI()).getScalarSizeInBits());
            ConstantInt *CI = ConstantInt::get(IntN, Val, true);
            return buildConstant(Res, *CI);
          }

arsenm · July 10, 2023, 12:41pm

You’re looking at code that’s too early. The error is telling you the instruction wasn’t properly selected. The register banks need to be constrained to a real instruction with final register classes during the selection pass. You’ve somehow let a generic instruction get past selection