I was looking at the register allocator code and had a question about that:
CodeGen/RegAlloc/PhysRegAlloc.cpp implements a graph coloring register allocator for the Sparc back end. It requests target machine register information via a call to getRegInfo() which returns a class TargetRegInfo containing the required information. For the x86 target machine, this interface has not been implemented. Is an implementation of a x86-specific TargetRegInfo class the only piece of the puzzle missing for a graph coloring x86 allocator? Or are there other issues that need to be considered for the PhysRegAlloc allocator to work on the x86.
Unfortunately it is not practically feasible to add support for the graph
coloring register allocator to the X86 backend. The problem is that the
Sparc and X86 code generators use widely different representations for
machine code, and that the GC register allocator has some sparc specific
details built into it (also, the TargetRegInfo interface assumes a graph
coloring register allocator, so it is not a generic interface).
We are slowly working on bringing the two representations together so that
we can have a unified backend which is easily retargettable, but this is
still a ways off.
In the X86 code generator, Alkis has been working on tuning up his new
linear scan register allocator, so that will improve things. He too is
interested in graph coloring allocators... maybe he can say more.
I haven't looked at the graph coloring allocator for the sparc but I am most
likely going to attempt to implement a graph coloring allocator for the x86