I am working on a target that has some wide registers for certain special instructions. Similar in some degree to the 80-bit floating point registers.
I want these to be allocatable and so they are exposed as a set of named registers and a custom RegisterClass. That class is currently annotated with a wide machine type, such as “v8i64”.
There is no operational support anywhere else for these wide types except moving them to a set of general purpose registers which is a multi-instruction sequence.
I want to expose such a value via builtins and intrinsics. There is no expressivity problem here, it is easy to have intrinsics which take/return a v8i64 and the IR allows loads and stores of those values. Loads and stores of such value is lowered by SelectionDAG/LegalizeTypes to sequences of smaller loads and stores, which what I would want.
My problem is that with no change, I get an assertion failure in SplitVectoResult since it does not know how to split the intrinsic. And if course split the intrinsic is not what is desired. Using TargetLoweringBase::setOperationAction for intrinsics to Legal for the type did not change since the result type is not legal.
I tried, announcing the register class with TargetLoweringBase::addRegisterClass for the specified v8i64 type, then LegalizeTypes stops lowering the load and store operations.
Perhaps this approach is wrong and I need to add a new MVT and plumb that through the intrinsics although that seems quite invasive.
Is there a good example for me to mimic?