Guidance regarding RISCV Vector Intrinsic

Hi !

I am a beginner in LLVM and trying to explore the riscv vector intrinsics. So far, I tried but was not able to locate any helpful material regarding the intrinsics. If any of the experts can guide me with where to start from and how to carry the intrinsic exploration, it will be a great lead for me. Moreover, if anyone could refer me some helping material, it would be great.

Regards
Kamran

What have you looked for so far and what are you trying to do? “explore the riscv” intrinsics is a bit vague…
Extending LLVM: Adding instructions, intrinsics, types, etc. — LLVM 16.0.0git documentation is the generic doc for intrinsics, but it won’t say anything specific about RISC-V.

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The thing I want to explore is how and where does the LLVM decides vsetvli on the basis of intrinsics.

Moreover, what is the flow of builtin functions defined in clang/include/clang/Basic/riscv_vector.td . What I want to ask is that does these functions automatically link with the intrinsics defined in llvm/include/llvm/IR/IntrinsicsRISCV.td? Or should some changes be made in some other files ? If so, which files need to be ammended?

If you just want to see how the intrinsics are implemented, just grep for them across the source tree like anything else.

First of all, I think you need to find the answer of who is the consumer of riscv_vector.td and what is the output after riscv_vector.td is processed. Before digging into the RISC-V intrinsic implementation, I think it is a good start to have a look at “TableGen Programmer’s Reference” (1   TableGen Programmer’s Reference — LLVM 16.0.0git documentation).

You can think riscv_vector.td is a kind of “database” of RISC-V vector intrinsics. All the information we need during the compilation is recorded in the file. The consumer of the “database” is called “TableGen backend”. The implementation is located in clang/utils/TableGen/RISCVVEmitter.cpp for RISC-V vector. Currently, there are three kinds of TableGen backends for RISC-V vector intrinsics, gen-riscv-vector-builtins, gen-riscv-vector-builtin-codegen, and gen-riscv-vector-header.

You want to know how the Clang builtins are converted to LLVM IR intrinsics. You can take a look at what is the output of gen-riscv-vector-builtin-codegen. In the generated file of this TableGen backend, there is main logic how to convert Clang builtins to LLVM IR intrinsic calls.

https://hx-software.feishu.cn/docs/doccn1WelHCsB6iD5O7oe3TMV6b
I have written this material from my own operance when I add one particular intrinsic.
Sorry for the simple Chinese version.