Handling far branches with fixups or ELF relocs

Denis,

thanks for your review of how different backends handle branch expansion. I went a little further and derived this table from the sources. There is also the BranchRelaxation MachineFunctionPass in ./CodeGen/BranchRelaxation.cpp which 4 passes use. This may be the “small jumps to larger jumps” pass you’re looking for.

AArch64/ no relaxInstruction BranchRelaxationPassID
AMDGPU/ relaxInstruction BranchRelaxationPassID both relax + pass
ARC/ no relaxInstruction ARCBranchFinalize
ARM/ relaxInstruction
AVR/ no relaxInstruction BranchRelaxationPassID
BPF/ no relaxInstruciton
Hexagon/ relaxInstruction HexagonBranchRelaxation both relax + pass
Lanai/ no relaxInstruction
MSP430/ no relaxInstruction MSP430BSel
Mips/ no relaxInstruction MipsBranchExpansion
NVPTX/ no relaxInstruction
PowerPC/ no relaxInstruction PPCBSel
RISCV/ relaxInstruction BranchRelaxationPassID both relax + pass
Sparc/ no relaxInstruction
SystemZ/ no relaxInstruction SystemZLongBranch
VE/ no relaxInstrcution
WebAssembly/ no relaxInstruction
X86/ relaxInstruction
XCore/ no relaxInstruction