Handling floating point exceptions in RISC-V using compiler

Hi,

I am interested in handling floating point exceptions for a RISC-V hardware.RISC-V ISA does not mandate generating interrupts when any floating point exception occurs. Only corresponding bit in floating point control and status register is set when any floating point exception occurs.

So, i want compiler to add checks for floating point exceptions.

I think this requires changing how a compiler performs some basic operations.

After every operation which may lead to floating point exceptions like addition and multiplication, status bits in FPCSR register should be checked and branching should occur if any of the bits is set.

I plan to make these changes in llvm for RISC-V and then do the same for gcc for RISC-V. This most likely will result in making things slow( significantly ) as number of assembly instructions will increase.

I guess that changes has to be made in the code responsible for generating assembly from RTL. It would be very helpful if i can get some hints on how should i proceed.

Faisal Riyaz

Hi Faisal. By default, LLVM will perform transformations with the
assumption that floating point exceptions are ignored (see
https://llvm.org/docs/LangRef.html#floating-point-environment). So
even if you altered the lowering for FP operations to check FPCSR, it
would be non-exhaustive. I recommend looking at the constrained
floating point intrinsics, which by my understanding would be a better
starting point for the sort of lowering you're describing
LLVM Language Reference Manual — LLVM 16.0.0git documentation

Are you using the Clang frontend? I don't know if there's been new
updates since <https://lists.llvm.org/pipermail/llvm-dev/2018-May/123529.html&gt;,
but you'll want Clang to support -ftrapping-math which I don't think
it does yet.

Best,

Alex