help/hints/suggestions/tips please: how to give _generic_ compilation for a particular ISA a non-zero LoopMicroOpBufferSize?

Dear all,

Some benchmarking experimentation I`ve done recently -- all on AArch64 -- has shown that it might be beneficial for all AArch64 targets to have a positive LoopMicroOpBufferSize, whereas the default that applies to all ISAs seems to be zero.

Although I`ve tried going as far down the rabbit hole as I can, I haven`t found a way to set DefaultLoopMicroOpBufferSize on a per-ISA basis or to change the generic AArch64 model. I`ve searched for anything that might create an ISA-specific default scheduling model or that might initialize the default MCSchedModel in an ISA-specific way, but I`ve come up empty.

The closest I found to what I was looking for seems to be a barrier for what I am trying to do; quoting "lib/Target/AArch64/AArch64GenSubtargetInfo.inc" in a build dir.:

     { "generic", (const void *)&NoSchedModel },

   [...]

   static const llvm::MCSchedModel NoSchedModel = {
     MCSchedModel::DefaultIssueWidth,
     MCSchedModel::DefaultMicroOpBufferSize,
     MCSchedModel::DefaultLoopMicroOpBufferSize,

... where "NoSchedModel" seems to be generated from this TableGen code in the source-tree file at "llvm/lib/Target/AArch64/AArch64.td":

   def : ProcessorModel<"generic", NoSchedModel, [
                      FeatureCRC,
                      FeatureFPARMv8,
                      FeatureNEON,
                      FeaturePerfMon,
                      FeaturePostRAScheduler
                      ]>;

... wherein it`s obvious how to add something like "FeatureCustomCheapAsMoveHandling" to the list of features, but I have no idea how to change the LoopMicroOpBufferSize, default or otherwise.

Furthermore, "NoSchedModel" seems to be a cross-ISA entity that is defined by code generated from this snippet of "llvm/include/llvm/Target/TargetSchedule.td":

   def NoSchedModel : SchedMachineModel {
     let NoModel = 1;
     let CompleteModel = 0;
   }

... which is made the default model in code generated from this snippet of "llvm/include/llvm/Target/Target.td":

   class Processor<string n, ProcessorItineraries pi, list<SubtargetFeature> f> {

   [...]

     SchedMachineModel SchedModel = NoSchedModel;

So, all in all, given the current structure of this part of LLVM, there seems to be no way to make a particular ISA have defaults different than the global defaults, and in AArch64 I can`t see a way to make the generic model different from the default model.

If editing "AArch64GenSubtargetInfo.inc" was a decent way of changing the generic model, I guess I would not need any help/etc. on this topic, but I`m pretty sure that editing "AArch64GenSubtargetInfo.inc" cannot possibly be the basis of a good patch proposal. [Maybe it won`t even work for an experiment -- I haven`t tried it yet.]

Regards,

Abe

Dear all,

Some benchmarking experimentation I`ve done recently -- all on AArch64 -- has shown that it might be beneficial for all AArch64 targets to have a positive LoopMicroOpBufferSize, whereas the default that applies to all ISAs seems to be zero.

Would it be the same positive value for all cores?

You could bypass the mechanism entirely and just override TTI::getUnrollingPreferences in the target.

   -Hal