Help: Instruction Pattern Matching question

Hello,
I am having some trouble matching patterns in targetinstructioninfo.td file with the CodeGen expectation. Could anybody please help?
Here is the example:

I want to emit instruction for adding 2 different kind of oprands. Basically i want to mix register types when I define the instruction for add,sub etc

I define the instruction TargetInstruction.td as follows:

class MyInst
<opcode op,subopcode subop,
dag outs, dag ins, string asmstr,list<dag> pattern>
Instruction
{
  let Namespce = "MyNameSpace";
  MyOpCode myop = op;
  MySubOpcode mysubop = subop;
  dag OutOprandList = outs;
  dag InOprandList = ins;
  let ASMString = asmstr;
  let Pattern = pattern;
}

def My_ADDINST1: MyInst <MYADD1, NO_SUBOP,
     (outs ptr_rc: $dest), (ins: $ptr_rc:$ptr1, Int32RC:$src)
     "myadd1 $dst, $ptr1, $src1",
     [(set $ptr_rc:$dst,(add $ptr_rc:ptr1, Int32RC:$src))]>;

it is giving me error like impossible to select.
Could anybody help me resolve this issue. Any example would be highly appreciated.

Hello,
I am having some trouble matching patterns in targetinstructioninfo.td file with the CodeGen expectation. Could anybody please help?
Here is the example:

I want to emit instruction for adding 2 different kind of oprands. Basically i want to mix register types when I define the instruction for add,sub etc

I define the instruction TargetInstruction.td as follows:

class MyInst
<opcode op,subopcode subop,
dag outs, dag ins, string asmstr,list<dag> pattern>
Instruction
{
let Namespce = "MyNameSpace";
MyOpCode myop = op;
MySubOpcode mysubop = subop;
dag OutOprandList = outs;
dag InOprandList = ins;
let ASMString = asmstr;
let Pattern = pattern;
}

def My_ADDINST1: MyInst <MYADD1, NO_SUBOP,
    (outs ptr_rc: $dest), (ins: $ptr_rc:$ptr1, Int32RC:$src)
    "myadd1 $dst, $ptr1, $src1",
    [(set $ptr_rc:$dst,(add $ptr_rc:ptr1, Int32RC:$src))]>;

it is giving me error like impossible to select.
Could anybody help me resolve this issue. Any example would be highly appreciated.

You need to provide a lot more information. e.g. What exactly is the error? Did you see the error during build time or when you run llc? What's the test case?

Evan

\(outs ptr\_rc: $dest\), \(ins: $ptr\_rc:$ptr1, Int32RC:$src\)
&quot;myadd1 $dst, $ptr1, $src1&quot;,
\[\(set $ptr\_rc:$dst,\(add $ptr\_rc:ptr1, Int32RC:$src\)\)\]&gt;;

it is giving me error like impossible to select.
Could anybody help me resolve this issue. Any example would be highly appreciated.

I assume that both ptr_rc and Int32RC are register classes of type
i32. There are no register classes at isel time => it's not possible
to distinguish operation within 'normal' i32 register class Int32RC
and pointer register class.

That's why tablegen asserts - it's seeing two identically operations.
Surely the second one is impossible to select.