Hexagon and choosing of slots

I’m curious how does hexagon hardware decide which slot to use for a given instruction? Is there special hardware to make that decision? I’m asking because I didn’t see any information about which slot to use for a given packet. Is it even possible to pass this kind of information through assembly? Say hardware sees a packet and the packet tells it which slot to use.

I would greatly appreciate any comments on this.

On Hexagon, the slot assignment is determined by the layout of the instructions in memory. The order of the instructions in the packet does not matter either in the IR, nor in the .s file, but it does when the packet is encoded into the actual machine code. In LLVM, the Hexagon shuffler orders the instructions just prior to encoding.

Specifically, the instructions in the packet are encoded "in reverse", i.e. the instruction that will go to the highest slot will be encoded first, then the instruction that will go to the second highest slot, etc. In case of a packet with 4 instructions, it will be
   addr: slot3
   addr+4: slot2
   addr+8: slot1
   addr+12: slot0
Not all slots have to be occupied. If they are not, the hardware will assign the slots based on the instruction, but within a packet the slots must be in a decreasing order. For example:
   addr: slot2
   addr+4: slot0
is ok, but
   addr: slot1
   addr+4: slot0
is not.

There are also bits in each encoding word that indicate the end of the packet: those must also be set properly by the compiler.

-Krzysztof

Error. ^This one is actually ok, I meant:

addr: slot0
addr+4: slot1

The hardware will verify that a given instruction may actually execute in a given slot, and if not, it will generate an exception.

-Krzysztof

Thanks!

On Hexagon, the slot assignment is determined by the layout of the
instructions in memory. The order of the instructions in the packet does
not matter either in the IR, nor in the .s file, but it does when the
packet is encoded into the actual machine code. In LLVM, the Hexagon
shuffler orders the instructions just prior to encoding.

Specifically, the instructions in the packet are encoded "in reverse",
i.e. the instruction that will go to the highest slot will be encoded
first, then the instruction that will go to the second highest slot, etc.
In case of a packet with 4 instructions, it will be
  addr: slot3
  addr+4: slot2
  addr+8: slot1
  addr+12: slot0
Not all slots have to be occupied. If they are not, the hardware will
assign the slots based on the instruction, but within a packet the slots
must be in a decreasing order. For example:
  addr: slot2
  addr+4: slot0
is ok, but
  addr: slot1
  addr+4: slot0
is not.

There are also bits in each encoding word that indicate the end of the
packet: those must also be set properly by the compiler.

-Krzysztof

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Would you mind pointing me to the source code where actual shuffling
occurs. I looked through lib/Target/Hexagon but was not able to find it. Is
shuffling now part of a core code?

Thanks,

The actual slot assignment is implemented here:
lib/Target/Hexagon/MCTargetDesc/HexagonShuffler.cpp

Here is a wrapper class used in MC:
lib/Target/Hexagon/MCTargetDesc/HexagonMCShuffler.cpp

-Krzysztof

Thanks!!! I also know why I wasn't able to find the shuffler. I'm working
with LLVM 3.5 (at the moment I'm locked into it) and Hexagon target doesn't
have the shuffler in it.