Hexagon, DFAPacketizer and instruction expansion

I’m using a Hexagon’s packetizer as an example to packetize instructions for my custom VLIW. The problem that I’m facing is that my target as it turns out doesn’t have all the instructions expanded by the time packetization happens (for example I have a RET instruction which gets expanded into a write to a register and a jump/branch). I’m wondering if Hexagon is experiencing the same issue and how it is solved? And if it doesn’t experience the same what would be the recommendation on solving this problem? At the moment, my packetization pass is the last one in MyTargetPassConfig::addPreEmitPass()

Any help is appreciated.

There is a target-independent pass that will try to expand all pseudo instructions after register allocation. For each instruction, it will check if the instructions is a pseudo-instruction, and if so, it will call the target hook "expandPostRAPseudo" on that instruction.

Your target will need to implement TargetInstrInfo::expandPostRAPseudo, and mark RET as a pseudo-instruction.

See lib/CodeGen/ExpandPostRAPseudos.cpp for the expanding pass, and the "expandPostRAPseudo" functions for individual targets to get an idea of how they work.


I guess I should be more clear by what I mean "expanded". When I say
"expanded" I mean the final instruction assembly representation, i.e. all
instructions were lowered to their assembly level. Will you recommendation
still hold or I should be considering another approach?

For dealing with cases like the RET instruction you described earlier---yes, the post-RA pseudo instruction expansion is the right place to do it.


Sorry to butt in … but curious …

“a RET instruction which gets expanded into a write to a register and a jump/branch”

If you do that after Register Allocation then where do you get the temporary register from? Not knowing the architecture in question at all, maybe there’s a dedicated one, in which case fine. But if not?

You can use the RegisterScavenger to get registers post-RA (which might introduce additional spills if you've run out of regs completely).


I was wrong. This was an assumption as I didn't know where I can check it.
Turns out it expand only to a jump instruction.