How to add Loongson ISA for Mips target?

Hi LLVM developers,

GCC[1] is able to use Loongson ISA[2] for instruction selection:

$ cat hello.c
#include <stdio.h>

int main(int argc, char *argv) {
   printf("Hello World\n");
   return 0;
}

$ gcc -O0 -S hello.c

$ cat hello.s
     .file 1 "hello.c"
     .section .mdebug.abi64
     .previous
     .nan legacy
     .gnu_attribute 4, 1
     .abicalls
     .rdata
     .align 3
.LC0:
     .ascii "Hello World\000"
     .text
     .align 2
     .globl main
     .set nomips16
     .set nomicromips
     .ent main
     .type main, @function
main:
     .frame $fp,48,$31 # vars= 16, regs= 3/0, args= 0, gp= 0
     .mask 0xd0000000,-8
     .fmask 0x00000000,0
     .set noreorder
     .set nomacro
     daddiu $sp,$sp,-48
     gssq $31,$fp,32($sp)
     sd $28,24($sp)
     move $fp,$sp
     lui $28,%hi(%neg(%gp_rel(main)))
     daddu $28,$28,$25
     daddiu $28,$28,%lo(%neg(%gp_rel(main)))
     move $2,$4
     sd $5,8($fp)
     sll $2,$2,0
     sw $2,0($fp)
     ld $2,%got_page(.LC0)($28)
     daddiu $4,$2,%got_ofst(.LC0)
     ld $2,%call16(puts)($28)
     move $25,$2
     .reloc 1f,R_MIPS_JALR,puts
1: jalr $25
     nop

     move $2,$0
     move $sp,$fp
     gslq $31,$fp,32($sp)
     ld $28,24($sp)
     daddiu $sp,$sp,48
     j $31
     nop

     .set macro
     .set reorder
     .end main
     .size main, .-main
     .ident "GCC: (GNU) 4.9.3 20150626 (Red Hat 4.9.3-8)"

gssq and gslq are some instructions of Loongson ISA. How to add Loongson ISA for Mips target?

I just:

* add loongson3a cpu in frontend https://github.com/xiangzhai/clang/commits?author=xiangzhai

* initial Loongson3A subtarget skeleton.

Are there some documents or papers? Please teach me, thanks a lot!

1. GitHub - loongson-community/gcc: GCC source tree for Loongson
2. Chinese Simplified version 龙芯中科技术股份有限公司

Hi,

LLVM MIPS backend now supports different MIPS ISA like mips1, mips2,
mips3, mips32, mips32r6 etc. If Loongson ISA just add a few new
instructions I think you do not have to add a new subtarget. Take a
look at MipsInstrInfo.td file. In that file there are multiple
ISA_MIPSxxx classes. Take for example ISA_MIPS3 and search it through
*.td files. Here is an example of instruction definition specific to
mips3:
[[
  def DMTC1 : MTC1_FT<"dmtc1", FGR64Opnd, GPR64Opnd, II_DMTC1,
              >, MFC1_FM<5>, ISA_MIPS3;
]]

More general and complete guide can be found here:
http://llvm.org/docs/WritingAnLLVMBackend.html

  • my old email address.

The ISA_* classes might not be the best choice for this. There’s an overall hierarchy and ordering to the ISA_* classes since they represent the generations of the MIPS ISA. If these extensions are available in Loongson chips based on MIPS32r1 and MIPS32r2 for example, it becomes difficult to describe with ISA_* classes without duplicating instruction definitions or setting up complicated subsets (like we had to for MIPS32r6 to deal with the instruction removals).

I would recommend the ASE_* classes which are intended for application specific extensions. These are used for optional extensions to the MIPS ISA such as MSA or DSP, but are also used for vendor specific extensions to the MIPS ISA such as cnMIPS. The ASE_CNMIPS class and the Proc<“octeon”, …> record are good examples that show how Cavium’s extensions to the MIPS ISA were included.

Hi Simon,

Thanks for your teaching!

As an apprentice in the backend, I just followed AVRSubtarget and ARMSubtarget:

https://github.com/xiangzhai/llvm/commits?author=xiangzhai

So I thought there might also need Loongson3A subtarget:

I just copied the MipsInstrInfo.td and renamed to Loongson3AInstrInfo.td, and implemented some load and store LoongExt64 instructions for ISA_LOONGSON class:

let AdditionalPredicates = [NotInMicroMips] in {
def GSLDLE : LoadMemory<"gsldle", GPR64Opnd, mem_simmptr, load, II_GSLDLE>,
LW_FM<0x16>, ISA_LOONGSON;
def GSLDGT : LoadMemory<"gsldgt", GPR64Opnd, mem_simmptr, load, II_GSLDGT>,
LW_FM<0x17>, ISA_LOONGSON;
def GSSDLE : StoreMemory<"gssdle", GPR64Opnd, mem_simmptr, store, II_GSSDLE>,
LW_FM<0x16>, ISA_LOONGSON;
def GSSDGT : StoreMemory<"gssdgt", GPR64Opnd, mem_simmptr, store, II_GSSDGT>,
LW_FM<0x17>, ISA_LOONGSON;
}

There are about 14 load and store, 13 arithmetic && logic operations LoongExt64 instructions, not including LoongExt32 and binary translation ISA.

But I have a requirement:
* If $ llc -mtriple=mips64el-redhat-linux -mcpu=mips64r2 helloworld.ll it only codegen generic MIPS64 ISA;
* If $ llc -mtriple=mips64el-redhat-linux -mcpu=loongson3a helloworld.ll not only codegen generic MIPS64 ISA, but also Loongson ISA to take place of *some* MIPS64 ISA for optimization.
And in the `MipsTargetMachine::getSubtargetImpl` function, it is able to get `+loongson3a` CPU when using -mcpu=loongson3a, perhaps is there some opportunity to hack the FS to distinguish the two cases? Furthermore, I have no idea whether or not tablegen support such requirement, or it needs to write some custom code based on SelectionDAG. So I need to read `Writing an LLVM Backend` document and other targets' source code more carefully :slight_smile:

Hi Daniel,

Thanks for your kind response!

Loongson 3A3000 is based on MIPS64r2

I will look at ASE_* class, thanks for your teaching!

And please point out my fault about my requirement http://lists.llvm.org/pipermail/llvm-dev/2018-September/125895.html

Hi Daniel,

Thanks for your kind response!

Loongson 3A3000 is based on MIPS64r2

Loongson - Wikipedia

I will look at ASE_* class, thanks for your teaching!

And please point out my fault about my requirement http://lists.llvm.org/pipermail/llvm-dev/2018-September/125895.html

But I have a requirement:
* If $ llc -mtriple=mips64el-redhat-linux -mcpu=mips64r2 helloworld.ll it only codegen generic MIPS64 ISA;
* If $ llc -mtriple=mips64el-redhat-linux -mcpu=loongson3a helloworld.ll not only codegen generic MIPS64 ISA, but also Loongson ISA to take place of *some* MIPS64 ISA for optimization.
And in the `MipsTargetMachine::getSubtargetImpl` function, it is able to get `+loongson3a` CPU when using -mcpu=loongson3a, perhaps is there some opportunity to hack the FS to distinguish the two cases? Furthermore, I have no idea whether or not tablegen support such requirement, or it needs to write some custom code based on SelectionDAG. So I need to read `Writing an LLVM Backend` document and other targets' source code more carefully :slight_smile:

I'm not entirely clear what your requirement is. Are the instructions in the Loongson3A additions to the MIPS ISA or are there instructions from the MIPS ISA that it removes? Assuming it's just additions then declaring the feature (see HasCnMips), the ISA_* or ASE_* class that uses that feature, the processor (see 'Proc<"octeon", ...>'), and the new instructions with an appropriate Pattern and ISA_*/ASE_* class (which you seem to have done, although I have no means of checking your pattern matches the behaviour of your instruction) is enough to make them available to the instruction selector. Most likely, your new patterns either aren't matching or something else is being chosen first.

The first thing to check is whether the instructions appear in the tablegen-erated MipsGenDAGISel.inc. If they are, then I suggest using -debug to trace the instruction selectors path through the MatcherTable from that file. This should reveal why it didn't pick your instruction.

Hi Daniel,

Thank you so much! I will follow the FeatureCnMips and hasCnMips() implementation way :slight_smile: And I also need to read document and other targets' source code more carefully!

In the initial Loongson3A subtarget skeleton,

https://github.com/xiangzhai/llvm/commit/c54d60e82c3f572c9c3cb2824d25c92e3a241446

There are:

* FeatureLoongson3A;

* if (hasLoongson3A()) { lowering to Loongson ISA; }

And simple pseudo code to meet my requirement, for example:

if (hasLoongson3A()) {
   gssdx(SrcReg, AT, IdxReg, 0);
} else {
   daddu(AT, AT, IdxReg);
   sd(SrcReg, AT, 0);
}

So I need a switch,

* switch ON: $ llc -mtriple=mips64el-redhat-linux -mcpu=loongson3a helloworld.ll

* switch OFF: $ llc -mtriple=mips64el-redhat-linux -mcpu=mips64r2 helloworld.ll

----- 8< -------- 8< -------- 8< -------- 8< -------- 8< -------- 8< ---

Loongson ISA, in the chapter 2.5 龙芯中科技术股份有限公司

It is additions to the MIPS64 ISA:

* 55+ LoongExt32/LoongExt64 load and store instructions;

* 43+ arithmetic and logic instrucitons;

* Binary translation instructions;

* Multimedia instrutions;

OpenJDK8 MIPS porting supports Loongson ISA Current Status of OpenJDK 8 for mips64el

For example,

$ java -Xcomp -XX:+UseLoongsonISA -XX:+PrintAssembly -version

It will JITted MIPS64 + Loongson ISA code.

But it is also able to work for generic MIPS64 ISA, for example,

$ java -Xcomp -XX:-UseLoongsonISA -XX:+PrintAssembly ...

It passed the tested on Debian qemu-system-mips64el http://hg.loongnix.org/jdk8-mips64-public/hotspot/rev/e9c6bf40f656