How to affect registers to make macro fusion happen

Take this as an example : :gear: D128393 [RISCV] Add macrofusion infrastructure and one example usage. (
LUI and ADDI can fusion only when

 Register FirstDest = FirstMI->getOperand(0).getReg();
 SecondMI.getOperand(1).getReg() == FirstDest
 SecondMI.getOperand(0).getReg() == FirstDest

Are there any good ways, maybe something working in the register allocation phase, to help facilitate this condition?

You could set register allocation hints to help with this. AMDGPU uses register hints for a somewhat similar purpose (if condition registers are allocated to VCC, a smaller instruction encoding can be used)

Thanks. I will go see how it works and try to use it to solve my problem.