How to avoid register reuse in machine instructions?

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1

Is there a way to force the register allocator to avoid reusing an operand register for a definition? For example, the following machine instruction reuses a register for the first operand and definition:

%uI7<def> = eq@III %uI7<kill>, %uI4

I'd like:

%uI8<def> = eq@III %uI7<kill>, %uI4

I'm guessing that the right way to do this would be to kill the operand registers after the given machine instruction rather than before it, but I don't see a way to mark it this way.

Andrew

2

Hello,

I'm guessing that the right way to do this would be to kill the operand
registers after the given machine instruction rather than before it, but
I don't see a way to mark it this way.

Right now the only way is to mark output reg as earlyclobber (see ARM
backend for examples).
Note that post-RA scheduler is not yet aware about earlyclobber
operands and thus can break the constraint.

3

That solved it, thank you!