How to compile chisel to HW?

Incubator CIRCT
1

Hi everyone,

I have a question regarding the chisel project, like XiangShan. As far as I know, the project generates verilog codes by default. However, I am interested in obtaining the HW dialect for analysis purposes. Can anyone provide me with some guidance on how to achieve this?

Thank you very much in advance!

2

Hi! You can get HW dialect by using compiler option -ir-hw instead of -verilog or -split-verilog. I’m not familiar with XiangShan codebase but apparently these are the lines you might want to hack: XiangShan/Makefile at 047e34f9536258d2008cf19a60dd3e6a9fa1d88a · OpenXiangShan/XiangShan · GitHub

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3

Thank you so much! I will try this option.

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