how to define extending vector load patterns?

I have an operation which loads a 16 bit block of data as 2 8-bit elements, sign extends the both parts to 32 bits and stores the result into 64-bit vector register.

How can I define the pattern for this?

just using [(set V2I32Regs:$result, (sextloadv2i8 ADDRrr:$address))]

gives me error that extloav2i8 is not defined.
(the same principle works for scalar sextload)

So I need to define it from the SDNodes? But how? there is no SDNode for extload? it's load with some extra parameters?

Hi Heikki,

just using [(set V2I32Regs:$result, (sextloadv2i8 ADDRrr:$address))]

gives me error that extloav2i8 is not defined.

I don't have a target to test this on, but looking at
include/llvm/Target/TargetSelectionDAG.td, there is an "sextloadvi8"
PatFrag, at least. I'd suggest a pattern along the lines of:

(set V2I32Regs:$result, (v2i32 (sextloadvi8 ADDRrr:$address)))

Tim.

Thanks, now it accepts the pattern, but it still does not work.

LLVM ERROR: Cannot select: 0x1b98410: v2i32,ch = load 0x2bc86a0, 0x1b9d460, 0x25ceb90<LD2[FIXED_STACK7](align=4), sext from v2i8>[ID=365]

(set V2I32Regs:$result, (v2i32 (sextloadvi8 ADDRrr:$address)))

Thanks, now it accepts the pattern, but it still does not work.

LLVM ERROR: Cannot select: 0x1b98410: v2i32,ch = load 0x2bc86a0, 0x1b9d460,
0x25ceb90<LD2[FIXED_STACK7](align=4), sext from v2i8>[ID=365]

Hmm. That's confusing, it looks like that really should match the
patten being used.

I'd add a "-debug" command-line option to llc and look at why the
match fails. It should print out the stages it goes through relative
to the table in XXXGenDAGISel.inc under the build directory. Hopefully
you'll see your pattern tried at some stage, and the line it failed at
should tell you why it didn't match.

The only guess I have is ADDRrr doing something funny, but the
debugging information should make things clearer.

Tim.