How to enable newly added registers to transfer args between basic blocks?

Hello all,
In my project,I declare a set of new vector register to represent related specific hardware unit for riscv backend.The codegen is fine when I use these register within one basic block.However,when I want to use these vector registers to transfer args between basic block within one function,something going wrong because LLVM alway chose to transfer args with GPR.Is there anything I can modify to enable direct transformation between basic blocks with my vector regs?Thank you!
Mike