> I've been watching this presentation from a 2014 LLVM dev meeting
Thanks for your sharing!
I am reviewing:
* The chapter 10 (Instruction Level Parallelism) and chapter 11 (Optimizing for Parallelism and Locality) of Compiler Principle
* Adding and Optimizing a Subtarget for MIScheduler by Dave Estes
* Scheduler for in-order processors - what's present and what's missing in LLVM by Javed Absar
* Writing Great Machine Schedulers by Javed Absar and Florian Hahn
Please leading me to implement Machine scheduling model for at least one core (e.g. Rocket, PULP)
Rocket - RV64G - "in-order", single-issue applicaEon core, BOOM - RV64G - "out-of-order", superscalar applicaEon core
So what about PULP? is it in-order or out-of-order?
Hi LLVM developers,
Welcome to review our work about porting GlobalISel to RISCV and give us some suggestion, thanks a lot!