how to lower MUL i64 for soft int arithmetic?

Dear, SelectionDAG developers, could you please comment on this issue
and clarify internals of MUL lowering?

Does my case (processor with soft MUL) supported by current design or
such architectures are out of scope? How lowering of large MUL is
supposed to work? What kind of minimalistic support should be provided
by target back-end? What can be used from current LegalizeDAG?

- Thanks, Sergey