How to make a StoreStore fence in IR?

IR & Optimizations
1

Is there a way to make a StoreStore fence in IR? The closest thing I found is fence release, but it’s is a StoreStore+LoadStore barrier, as far as I understand. I couldn’t find anything with just StoreStore semantics. According to The JSR-133 Cookbook, it should be a no-op on x86 and dmb st on ARM.

2

a suboptimal solution might be using target-specific intrinsics, like int_arm_dmb that models dmb

3

Note that given the way the memory model works, such a fence couldn’t be used as a barrier for non-atomic stores; a non-atomic “store” in IR performs an arbitrary sequence of machine load and store operations, so any loads could move past the barrier. It would only act as a barrier for atomic operations. Which is sort of niche.