how to prevent LLVM back-end from reordering instructions at instruction scheduling?

Hello,

I have a LLVM backend question regarding how to prevent compiler from reordering instructions. For example, I have the following instructions. Z_instruction is the one which I want to insert.

// instruction order which I am looking for
/////////////////////////////////////////
A_instruction
B_instruction

Z_instruction

C_instruction
D_instruction
E_instruction
F_instruction

Z_instruction

G_instruction
F_instruction

You can create a DAG mutation that adds artificial dependencies between A, B and Z.

-Krzysztof

I have the same issue, would it be easier and more useful to attach a flag to the instruction to tell the scheduler not to move instructions across this boundary?

-Ryan

Maybe I missed the point. But from the email, it is not clear to me what is the reason that what scheduler does is not good. We will need to decide on the solution after we understand the reason that the reordering is incorrect.

You can override TargetInstrInfo::isSchedulingBoundary for that.

-Krzysztof

I don’t want to hijack the OPs thread but for us, the issue is that we lay some intrinsics in the IR and want to pick them up in the backend post-scheduling and their placement matters.

Krzysztof,

Thanks, I’ll look into it.

-Ryan

Setting the MI as isTerminator should have the same impact, yes? I’m not sure of the other consequences of this though, if any, have to look into it.

Thanks.

-Ryan

Just a thought. What about putting a dummy barrier between the instructions during selectionDAG creation?

You’d think isBarrier might work but this is a sync mechanism and doesn’t prevent instructions from crossing the barrier that aren’t use dependent.