i1 types in MergeConsecutiveStores

Hello LLVM,

In DAGCombiner.cpp, MergeConsecutiveStores uses

int64_t ElementSizeBytes = MemVT.getSizeInBits()/8;

https://github.com/llvm-mirror/llvm/blob/master/lib/CodeGen/SelectionDAG/DAGCombiner.cpp#L10669

which is broken for i1 types where getSizeInBits() == 1. My
out-of-tree target hits this case and eventually LLVM asserts in
Type.cpp.

Is there some reason MergeConsecutiveStores should not expect to see i1 types?

Thanks,
-steve

From: "Steve King" <steve@metrokings.com>
To: llvmdev@cs.uiuc.edu
Sent: Monday, May 11, 2015 11:40:56 PM
Subject: [LLVMdev] i1 types in MergeConsecutiveStores

Hello LLVM,

In DAGCombiner.cpp, MergeConsecutiveStores uses

int64_t ElementSizeBytes = MemVT.getSizeInBits()/8;

https://github.com/llvm-mirror/llvm/blob/master/lib/CodeGen/SelectionDAG/DAGCombiner.cpp#L10669

which is broken for i1 types where getSizeInBits() == 1. My
out-of-tree target hits this case and eventually LLVM asserts in
Type.cpp.

Is there some reason MergeConsecutiveStores should not expect to see
i1 types?

My impression is that there are a lot of things that are (still) broken for i1 memory operations (and i1 vectors). Patches welcome.

-Hal

That seems likely, however this particular issue had already been fixed in r236927.