[ia64] Assertion failed: (!OpInfo.AssignedRegs.Regs.empty() && "Couldn't allocate input reg!")

All,

The following IR is causing the assert:

\begin{ll}
; ModuleID = 'x.bc'
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
target triple = "ia64-portbld-freebsd8.0"

define void @__ia64_set_fast_math() nounwind {
entry:
         tail call void asm sideeffect "mov.m ar.fpsr=$0", "r"( i64 2709527404217215 ) nounwind
         ret void
}
\end{ll}

(See gcc/config/ia64/crtfastmath.c)

In llvm::TargetLowering::getRegForInlineAsmConstraint(), the "r" constraint
(i.e. TargetLowering::C_RegisterClass) isn't handled and the function returns
<pair>(0, NULL). However, it is explicitly called for that constraint by
llvm::SelectionDAGLowering::visitInlineAsm():

   if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass)
     GetRegistersForValue(OpInfo, SawEarlyClobber, OutputRegs, InputRegs);

Assuming the correct fix is to enhance
llvm::TargetLowering::getRegForInlineAsmConstraint(), can someone give me
some pointers as to how to fix it? I have no experience with the code and
like to get my hands dirty...

Thanks,

BTW: Is there a cross-reference of the project somewhere?

[correction]

All,

The following IR is causing the assert:

\begin{ll}
; ModuleID = 'x.bc'
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-
i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-
f80:128:128"
target triple = "ia64-portbld-freebsd8.0"

define void @__ia64_set_fast_math() nounwind {
entry:
        tail call void asm sideeffect "mov.m ar.fpsr=$0", "r"( i64
2709527404217215 ) nounwind
        ret void
}
\end{ll}

(See gcc/config/ia64/crtfastmath.c)

In llvm::TargetLowering::getRegForInlineAsmConstraint(), the "r"
constraint
(i.e. TargetLowering::C_RegisterClass) isn't handled and the function
returns
<pair>(0, NULL). However, it is explicitly called for that constraint by
llvm::SelectionDAGLowering::visitInlineAsm():

It's llvm::TargetLowering::getRegClassForInlineAsmConstraint() that
returns an empty vector and thus is the root case of the assert.

It seems that llvm::TargetLowering::getRegForInlineAsmConstraint()
is supposed to work on a single (physical) register.

In GetRegistersForValue() is the following:

3817 // This is a reference to a register class that doesn't directly correspond
3818 // to an LLVM register class. Allocate NumRegs consecutive, available,
3819 // registers from the class.
3820 RegClassRegs = TLI.getRegClassForInlineAsmConstraint(OpInfo.ConstraintCode,
3821 OpInfo.ConstraintVT);

Is it me or is the comment not really applicable to this particular
case?

thanks,

The following IR is causing the assert:

The issue here is that the IA64 backend doesn't have inline asm support yet. This should be pretty easy to add. Take a look at the X86 version:
X86TargetLowering::getRegForInlineAsmConstraint

it just maps "r" onto the GPR register class, itanium should do something similar.

Is it me or is the comment not really applicable to this particular
case?

Right. The issue is that the target didn't return info about what it is, so the generic code is trying to guess :). The code at the end of the X86/X86ISelLowering.cpp file should be a good place to start, or the ARM backend or PPC which are somewhat simpler.

-Chris

The following IR is causing the assert:

The issue here is that the IA64 backend doesn't have inline asm support
yet. This should be pretty easy to add. Take a look at the X86 version:
X86TargetLowering::getRegForInlineAsmConstraint

I see. That is much more fundamental than what I figured...

Right. The issue is that the target didn't return info about what it is,
so the generic code is trying to guess :). The code at the end of the
X86/X86ISelLowering.cpp file should be a good place to start, or the ARM
backend or PPC which are somewhat simpler.

Thanks. I'll see if I can produce a patch.