ifconversion before register allocation

Hi all,

I am using llvm backend to generate binary for a specific accelerator. I would like to convert instructions into predicated form when instructions are still in SSA form. It looks like that ifconversion execution flow is different when instructions are in SSA form. However, I am encountering many problems (specially with registers) when I use it before register allocation. I was wondering if anybody could confirm that if-conversion can be used before register allocation? Any suggestion is really appreciated.

Thanks

Hi all,

I am using llvm backend to generate binary for a specific accelerator. I would like to convert instructions into predicated form when instructions are still in SSA form. It looks like that ifconversion execution flow is different when instructions are in SSA form. However, I am encountering many problems (specially with registers) when I use it before register allocation. I was wondering if anybody could confirm that if-conversion can be used before register allocation? Any suggestion is really appreciated.

EarlyIfConverter is the pass designed to run before RA. It is not enabled by default. It is quite different from the post-ra if-converter. It works on SSA and does not actually predicate instructions. It generates CMOVs.
—Andy

Andy,

I have already enabled EarlyIfConversion but as you said, it does not predicate instruction (only works for exception safe instructions).

Thanks
Mahdi

Andy,

I have already enabled EarlyIfConversion but as you said, it does not predicate instruction (only works for exception safe instructions).

Right, there is no in-tree machine IR pass that predicates instructions with virtual registers. You could do such a thing with a target specific pass, but the register coalescer, preRA scheduler, and RA are not predicate-aware. Before phi-elimination and register coalescing you would need some kind of select/cmov pseudo instruction. You could lower that instruction postRA, which would require copies—probably not what you want. Or you could coalesce the selects before regalloc and the register allocator will allocate predicated instructions conservatively (register operands appear live under all conditions).

-Andy