Immediate instructions / register allocator

Hi,

I tried transforming code that loads an immediate into a virtual register, and then uses that virtual register in various ways, into code that uses immediate operands instead.

To my surprise, this made the register allocator produce worse code in many cases. It seems that it is splitting live intervals and spilling more. In some cases the code was better.

I wonder how this could be? Generally, using the immediates directly as constant operands should decrease regpressure, right? How could the RA-algorithm have been mislead by this?

Thanks,

Jonas

Hi,

I tried transforming code that loads an immediate into a virtual register,
and then uses that virtual register in various ways, into code that uses
immediate operands instead.

I suspect a concrete example might be helpful in demonstrating the
specific issue.

Samsung R&D center at San Jose, CA, has a full time position open. The
focus will be to work on a Translator/Instrumenter/Validator for WebCL
kernels. The job description is attached for reference. People interested
in the position can send their information to me.

WebCL provides JavaScript bindings to OpenCL APIs, and the standard is
currently being defined by Khronos, under the WebCK working group. There
are currently three open source implementations of WebCL.

Noted below are some WebCL related resources:
The WebCL public draft can be found at:
https://cvs.khronos.org/svn/repos/registry/trunk/public/webcl/spec/latest/in
dex.html
Samsung's prototype (BSD license) source code:
http://code.google.com/p/webcl
Public WebCL distribution list: public_webcl@khronos.org

Regards,
Tasneem Brutch

GPGPU_Sr_Engineer_updated_10_19.docx (17.4 KB)