Hello.
I am implementing for my processor back end 2 loop instructions: set_loop_counter and Jump_if_counter_not_zero instruction (this is similar to PowerPC's CTR count register and MTCTR and BCTR instructions, which is implemented in the LLVM PowerPC back end, but I did not generate code for PPC with LLVM; see http://www.ibm.com/developerworks/library/l-powasm3/ for details).
For this I defined LLVM intrinsics: int_connex_repeat_x_times (for set_loop_counter) and int_connex_end_repeat (for Jump_if_counter_not_zero instruction).
But then, in TableGen it seems I cannot give jump semantics for the Jump_if_counter_not_zero instruction, because it is already an ASM intrinsic. More exactly, I give:
class END_REPEAT_DESC_BASE<InstrItinClass itin = NoItinerary> {
dag OutOperandList = (outs);
dag InOperandList = (ins);
string AsmString = "END_REPEAT; // END_REPEAT";
list<dag> Pattern = [(int_connex_end_repeat)];
bit hasSideEffects = 1;
InstrItinClass Itinerary = itin;
}
I should give ISD::BRCOND semantics to my Jump_if_counter_not_zero (Connex) ASM instruction in order for the back end to perform eventual optimizations on the code such as loop invariant code motion, etc.
Should I do this in the TableGen END_REPEAT_DESC_BASE spec by chaning the line:
list<dag> Pattern = [(int_connex_end_repeat)];
with
list<dag> Pattern = [(brcond targetAddress)];
Or should I maybe do this in [Target]ISelLowering or [Target]ISelDAGToDAG by adding there BRCOND instead of the int_connex_end_repeat machine-independent node?
Thank you,
Alex