Hi All,
I need to implement select_cc as a "cmp; mov rX,1; brcond cnd, END;
mov rX,0; END:" sequence.
Chris mentioned that the PPC code (as well as the x86 SSE code) does
this, but I can't seem to find it.
What I really need to kmow is how to insert the branch/label pair at
instruction selection phase.
Anyone have an example of this?
someguy wrote:
Hi All,
I need to implement select_cc as a "cmp; mov rX,1; brcond cnd, END;
mov rX,0; END:" sequence.Chris mentioned that the PPC code (as well as the x86 SSE code) does
this, but I can't seem to find it.What I really need to kmow is how to insert the branch/label pair at
instruction selection phase.Anyone have an example of this?
Add a pseudo instruction for the select with usesCustomDAGSchedInsteter = 1. Replace the pseudo instruction with the required control flow in the EmitInstrWithCustomInserter member of your ISelLowering class. There are examples of this in the MIPS or XCore backends.
-Richard
Yeah, I finally found the example in MIPS, but am now having an issue
with SELECT_CC/SETCC nodes.
Should lines 9 and 10 not be a select?
; ModuleID = '<stdin>'
target datalayout =
"e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:32:32"
target triple = "i386-unknown-linux-gnu"
define i32 @test(i32 %data, i32 %number) nounwind readnone {
entry:
%0 = shl i32 1, %number ; <i32> [#uses=1]
%1 = and i32 %0, %data ; <i32> [#uses=1]
%not. = icmp ne i32 %1, 0 ; <i1> [#uses=1]
%.0 = zext i1 %not. to i32 ; <i32> [#uses=1]
ret i32 %.0
}
define i32 @main(i32 %argc, i8** nocapture %argv) nounwind readnone {
entry:
%0 = tail call i32 @test(i32 10, i32 1) nounwind ; <i32> [#uses=1]
ret i32 %0
}
Thanks