IMUL x86 instruction

Hi,

The x86 CPU IMUL instruction has forms such as:
IMUL reg
EDX:EAX ← EAX ∗ reg

reg, EAX and EDX are 32bit registers.

How can I represent this sort of instruction in LLVM IR ?
It is really a 32bit * 32 bit = 64 bit, but no LLVM IR exists to do that.
Or, a similar question:
What LLVM IR would produce this IMUL instruction form?

For context, I am writing a x86 to LLVM IR decompiler, so wish to
represent IMUL in LLVM IR.

Kind Regards

James

For context, I am writing a x86 to LLVM IR decompiler, so wish to
represent IMUL in LLVM IR.

From a decompiler's perspective, it probably represents 3

instructions: 2 sexts (imul is the signed one, isn't it?) and a mul.
With the usual caveats you'll be dealing with over EFLAGS.

Cheers.

Tim.

I will take a bit more than that, if the following instructions only use edx.
Are there any llvm ir instructions that can break a 64bit value into 2 32bit values.

I will take a bit more than that, if the following instructions only use
edx. Are there any llvm ir instructions that can break a 64bit value into 2 32bit
values.

Those would be trunc and lshr. The low bits are simply a trunc of the
64-bit value; the high bits are a trunc of the 64-bit value shifted
right by 32 bits.

Cheers.

Tim.