Hello LLVM developers,
I've just uploaded a first-draft patch series into Phabricator which adds initial support for the Arm v8.1-M architecture, and in particular, the MVE vector architecture that is an optional part of 8.1-M.
The ISA spec that we've implemented to is public, and available at
There are two particular changes I should call out in this series for being potentially disruptive to existing functionality.
Firstly, in the Arm backend specifically, it's become inconvenient that the subtarget features 'fp-only-sp' and 'd16' have reversed sense, i.e. that they indicate the _removal_ of functionality instead of the addition. I've flipped them round and replaced them with new positive-sense features named 'fp64' and 'd32', so that the optional MVE feature and the optional double precision feature in 8.1-M can interact sensibly, without running into the problem that adding one of them to an MCSubtargetInfo is unable to remove the antifeature added by the other.
Secondly, I've added a feature to the ISel-related Tablegen back ends, to support MVE's extensive use of lane-by-lane predication in vector instructions. Every MVE instruction that can partially overwrite its destination register is modelled in MC as taking an input operand corresponding to the previous value of that register, which is tied to the output for register allocation purposes. When the instruction is used unpredicated, that operand has to be set to an undef / IMPLICIT_DEF node. So it's useful for ISel patterns to be able to set that as the default value of the operand. To arrange that, I've invented a thing called 'undef_tied_input' (similar to existing special names like 'zero_reg') which you can put in OperandWithDefaultOps to make that happen automatically.