inline assembly matching error

I’m trying to add support for inline assembly and I keep getting this error:

“:1:2: error: invalid instruction”

which is due to the fact that MatchInstructionImpl() returns Match_MnemonicFail.
This function is tablegen’ed in and for some reason it can’t find JAL even though I can clearly see it in both MatchTable0[] and MnemonicTable

The input was

int main ()


asm volatile (“JAL”);

return 0;


If I go to JAL’s definition in and change its assembly string from “JAL” to “jal”, it works.

How can I keep using uppercase characters? It seems to be a minor setting somewhere but can’t find it.


It's not a setting, I'm afraid. LLVM can assemble both upper & lower
case instructions (as long as you're careful), but the underlying
definition has to be in lower-case. The most obvious example of this
is lib/MC/MCParser/AsmParser.cpp:2182 (in function parseStatement)
where the mnemonic always gets "lower" called on it before it's handed
off to the target.



I’d like to know how this enum is generated

MatchClassKind {

InvalidMatchClass = 0,

OptionalMatchClass = 1,

MCK__MINUS_1, // ‘-1’

MCK_0, // ‘0’

MCK_1, // ‘1’

MCK_R0, // ‘R0’


MCK_CRegs, // register class ‘CRegs’

MCK_NRegs, // register class ‘NRegs’

MCK_ORegs, // register class ‘ORegs’

MCK_RA, // register class ‘RA’

MCK_SRegs, // register class ‘SRegs’

MCK_ZRegs, // register class ‘ZRegs’

MCK_CPURegs, // register class ‘CPURegs’


MCK_Imm, // user defined class ‘ImmAsmOperand’



I do not recognize register class RA. I do have a register named RA but it’s not a class.

Here is an excerpt from my with all the reg classes definitions

def CPURegs : RegisterClass< …

def CRegs : RegisterClass<…

def ORegs : RegisterClass<…

def NRegs : RegisterClass<…

def ZRegs : RegisterClass<…

def SRegs : RegisterClass<…

Where does MCK_RA come from?