Instruction selection bug for vector store with FixedStack

Hello.
     Could you please help me solve the following LLC bug happening at instruction selection time:
         ISEL: Starting pattern match on root node: t172: ch = store<ST64[FixedStack6]> t0, t6, FrameIndex:i64<6>, undef:i64

           Initial Opcode index to 157
           Skipped scope entry (due to false predicate) at index 162, continuing at 236
           Match failed at index 241
           Continuing at 263
         LLVM ERROR: Cannot select: t172: ch = store<ST64[FixedStack6]> t0, t6, FrameIndex:i64<6>, undef:i64
           t6: v8i64,ch = CopyFromReg t0, Register:v8i64 %vreg19
             t5: v8i64 = Register %vreg19
           t171: i64 = FrameIndex<6>
           t73: i64 = undef
         In function: foo

     I actually have difficulties in understanding in the Selection DAG what the FixedStack operand means. Also, it is not really clear for me how to handle it in my back end.

     Below follows and excerpt of the Selection DAG with the problem:
         Optimized legalized selection DAG: BB#16 'foo:vector.body34'
         SelectionDAG has 71 nodes:
           t0: ch = EntryToken
           t6: v8i64,ch = CopyFromReg t0, Register:v8i64 %vreg19
             t142: i64,ch = CopyFromReg t0, Register:i64 %vreg18
           t143: i64 = add t142, Constant:i64<8>
               t172: ch = store<ST64[FixedStack6]> t0, t6, FrameIndex:i64<6>, undef:i64
             t173: i64,ch = load<LD8[FixedStack6](align=64)> t172, FrameIndex:i64<6>, undef:i64
         ...
                       t127: ch = store<ST8[%aPtr.addr74]> t105:1, t109, Constant:i64<0>, undef:i64
                       t106: v8i64 = add t105, t79
                     t129: ch = store<ST64[inttoptr (i64 3 to <8 x i64>*)](align=8)(alias.scope=<0x20c8ea0>)(noalias=<0x20c8a80>,<0x20cd700>)> t127, t106, Constant:i64<3>, undef:i64
         ...

   Thank you,
     Alex

Hi Alex,

    I actually have difficulties in understanding in the Selection DAG what
the FixedStack operand means. Also, it is not really clear for me how to
handle it in my back end.

FixedStack refers to objects at a known location, created by
MachineFrameInfo::CreateFixedObject rather than allocated an arbitrary
stack slot. They're usually used for things like function parameters:
you know exactly where they are on the stack.

What you're seeing is the MachineMemOperand being printed. They
typically don't take part in instruction selection, the FrameIndex is
the most likely problem, though that's a bigger than average vector so
maybe it should have been split?

        Initial Opcode index to 157
         Skipped scope entry (due to false predicate) at index 162, continuing at 236
         Match failed at index 241
         Continuing at 263

Assuming you've written a pattern that you think should be able to
store a v8i64 (which ought to be enough, really), what I'd do now is
look at build/lib/Target/XYZ/XYZGenDAGISel.inc. You should be able to
correlate the debug info as above with your pattern and see just which
bit of it is failing. Hopefully that'll tell you how to fix it.

If I saw this on one of the in-tree targets I'd be suspicious that the
C++ code in SelectWhateverAddrMode (from XYZISelDAGToDAG.cpp) was
refusing to handle FrameIndex operands for the pointer (or maybe that
an Operand<i32> had been used for something that's really a pointer).
But you'll know more after looking at the .inc file.

Cheers.

Tim.