Instruction with same mnemonic but different encoding

Hi all,

Is there any way in llvm where the assembler can handle instructions with same name mnemonics but with different encodings? when there is slight change in the architecture. I came across the suggestion to use different decodernamespace but that doesn’t seem to work. Please guide.

Thanks,
Siddharth

Is there any way in llvm where the assembler can handle instructions with same name mnemonics but with different encodings? when there is slight change in the architecture. I came across the suggestion to use different decodernamespace but that doesn't seem to work. Please guide.

I'm not an expert on the subtleties here, but it does work for the AMDGPU backend.

You'll find that machine instructions come in multiple versions: pseudos that are used during most MIR passes, and then _si / _vi etc. suffixed versions corresponding to the generation-specific encoding.

So try comparing what you're doing with what's happening in AMDGPU, and that should hopefully give you some insight.

Cheers,
Nicolai