Instructions having variable names as operands

Hi there

You have asked me how my instruction set works.

If I code like this:

int foo1() { int x1,x2; ... ... int main () { int j; j = foo1(); }

This should be emitted like this:

Enter foo1; reg x2, x1 add 1;x1 Call foo2;x1,x2 Exit foo1; x2

Enter foo2; k reg temp0:1 cmp k,1;temp0 demultiplex m0;temp0;b1;b0
branch b0 add 2;k unbranch b0 branch b1 unbranch b1 mux m0 Exit
foo2; k

I am not sure about full source language scoping rules you
mentioned. Would you mind telling me about that? Thank you very
much.

Seung Jae Lee

it seems you target some sort of VM. Your target architecture has some
similarities to the relatively unknown ZIL that is mentioned in this
paper:
Mayur Naik and Jens Palsberg. Compiling with code-size constraints
<http://www.cs.ucla.edu/~palsberg/paper/tecs04.pdf&gt;\. /ACM
Transactions on Embedded Computing Systems/, 3(1):163-181, 2004. And
possibly to other (open-sourced) VMs as well. Another example is the
"old" SimpleSUIF code generator that emits three-address-code with
variables as operands AFAICR.

I have some questions regarding your target:

1) Related to what Chris Lattner asked you as well, do you permit
global variables in your target IS? Do you have notions for "static"
(or global) and "local" for scoping?
2) Do you use SSA? Plus: is it possible in LLVM for SSA to create
multiple copies of global variables? There are some recent papers
regarding various forms of "memory SSA" but i'm not sure how they deal
with this sort of stuff.
3) If having variables as operands can be done in LLVM, wouldn't this
require dealing with expanding "storages". How would that fit to
machine description conventions?
4) (If permitted) is your target a hard processor or a VM?

Kind regards
Nikolaos Kavvadias