Instructions with no operand

Hi all,

I am trying to implement an instruction with no operand for example “clr” in TableGen.

Guys, I stuck at this point. Could you please give me a hint how to solve this problem without touching the LLVM backbone?!

Why LLVM doesn’t let me define an instruction consisting of an operator with no operand?

Could you try it without the pattern? I.e. just this:

      class TestInst<string opc, string asmstr, dag oops, dag iops,
                     list<dag> pattern> : Instruction { ... }

      class ALU<string opc> : TestInst<opc, "", (outs), (ins)>;

See if you get the same error. I suspect it has to do with the intrinsic itself, not the instruction definition.


I found A solution.

Like the CLREX solution of AArch64.

I define an InstAlias, then add a default value to the “clr” instruction (i.e. clr 0) and then change may base calss to match this.

Thanks everyone.

Hi again,

I figured out the problem. Actually there is no problem with the TabelGen implementing instructions with no operand.

The problem with my code was that the class for my no-operand-operator was inhereted from a class which a a variable was assigned to some bit range that was no used/initiated in the new class. I don’t know exactly the nature of the problem, but when I accidentally changed the super class, I was able to define my instruction with no operand. As the compiler was telling me, there was like a flattening issue!!

Just wanted to tell this if anyone in the future is going to face it!