I am working on a project that requires me to suggest to the hardware simulator (gem5) switch cores from one to another at the start of certain basic blocks. Could someone advice me if I should go with introducing a new Intrinsic instruction for this purpose. I will be following http://llvm.org/docs/ExtendingLLVM.html for this. Gem5 has certain reserved op-codes which I can use.
I was thinking of adding the new instruction to Other Ops type but haven’t quite figured out the whole procedure yet. The instruction requires to have one intty argument (that can take values from 0-2) specifying the core type.
Any help or suggestions would be appreciated.
Graduate Student Research Assistant
University of Michigan
Since the steps on how to create a new instruction in http://llvm.org/docs/ExtendingLLVM.html point to files which are not present in LLVM 3.2, I looked at the diffs for a couple of new instructions (fence, resume etc) that were added some time back, to create my own SwitchCodeInst.
The following command works fine
opt -load /home/silkyar/Workspace/32b_llvm/llvm/Debug+Asserts/lib/LLVMTestSwitchCore.so -testswitchcore test.bc > test_new.bc
but conversion to assembly crashes with the following error -
llc: test_new.bc: error: Invalid ALLOCA record
While deleting: i32 %
Use still stuck around after Def is destroyed: switchcore i32 1
llc: Value.cpp:79: virtual llvm::Value::~Value(): Assertion `use_empty() && “Uses remain when a value is destroyed!”’ failed.
The code to insert the new instruction is straight forward -
Value* coreType = ConstantInt::get(llvm::Type::getInt32Ty(F.getContext()), 1);
Instruction* fnp = bbIter->getFirstNonPHI();
Could someone help me out with this? Does llc require certain files to be changed for the assembly which are not part of the diff for ‘ResumeInst’ that I followed