I am working on an out-of-tree target. I am wondering if it is possible to force the register allocator (and/or spiller) to not break certain instruction sequence.
phys_reg = MI1 vreg1
vreg 2 = MI2 phys_reg
Is there a way to tell RA/spiller not to insert COPY or spill between MI1 and MI2?
I am using greedy register allocator and inline spiller.
You can make a pseudo-instruction that corresponds to the combination MI1/MI2, then expand it into the actual instructions in TII::expandPostRAPseudo.
Thanks for the suggestion.
For my target making pseudo instructions for this is a bit too much, because there are many possible combinations. I tried making a bundle in this situation, and it seems to work fine (with a little bit hacking).