Is it possible to define a LLVM intrinsic that expands in more than one instructions ?

Hi all,

Is it possible to define a LLVM intrinsic that expands in more than one instructions ?

If yes, how ?

Best Regards

Seb

Sure, a back-end is free to expand an intrinsic into as many instructions as it wishes. You can define this in TableGen with a pattern:

def : Pat<(my_intrinsic Reg:$a, Reg:$b), (MyInst1 (MyInst2 Reg:$a), Reg:$b)>;

This would expand a call to @llvm.my_intrinsic(a, b) to:

r1 = MyInst2 $a
r2 = MyInst1 r1, $b