# Is it possible to tie two defs together?

For example, if you have something like:

vreg3 = LD operation
vreg4 = vreg2 * vreg1

Where I would like vreg3 and vreg4 to map to the same physical register?

Imagine that the second instruction has an implicit arithmetic operation tied to vreg 4 such that vreg4 is both an input and output and the initial value of vreg4 is loaded into vreg3, so such that vreg4 = vreg3.

Is this possible pre-regalloc?

Thanks.

For example, if you have something like:

....
vreg3 = LD operation
vreg4 = vreg2 * vreg1
...

Where I would like vreg3 and vreg4 to map to the same physical register?

Imagine that the second instruction has an implicit arithmetic operation
tied to vreg 4 such that vreg4 is both an input and output and the initial
value of vreg4 is loaded into vreg3, so such that vreg4 = vreg3.

I don't quite understand your explanation for how the instructions are
connected, but one way to solved this would be to represent both
instructions with a single pseudo instruction and then expand
it post-RA.

-Tom

This sounds like you want a tied operand constraint on the instruction definition. Indexed load/store operations which write back to the base register on ARM/AArch64 have a similar sort of thing, so you might have a look at those. It ends up looking something like,

let Constraints = “\$src1 = \$dst” in
def MyInst: … <(outs GPR:\$dst), (ins GPR:\$src1, GPR:\$src2, GPR:\$src3)> …

That is, you have separate operands, one for the output and one for the input, but the constraint tells regalloc that they’re actually the same in the instruction encoding, so they’ll always be allocated to the same physical register.

-Jim

Jim,

Yes, I believe this is what I’m looking for. I was looking at the x86 INC instruction as an example and this is what they used also. I’m assuming that the ‘Constraints’ implicitly adds the ‘tied’ registers?

Thanks.

Right. That constraint says that the register for operand “\$src1” must be tied to the register used for operand “\$dst”.

-Jim